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128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7636d 07h /can/tags/rel_18/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7636d 07h /can/tags/rel_18/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7637d 03h /can/tags/rel_18/
125 Synchronization changed, error counters fixed. mohor 7641d 09h /can/tags/rel_18/
124 ALTERA_RAM supported. mohor 7661d 15h /can/tags/rel_18/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7668d 21h /can/tags/rel_18/
119 Artisan RAMs added. mohor 7677d 18h /can/tags/rel_18/
118 Artisan RAM fixed (when not using BIST). mohor 7677d 18h /can/tags/rel_18/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7677d 18h /can/tags/rel_18/
115 Artisan ram instances added. simons 7683d 12h /can/tags/rel_18/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7710d 13h /can/tags/rel_18/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7712d 13h /can/tags/rel_18/
110 Fixed according to the linter. mohor 7712d 13h /can/tags/rel_18/
109 Fixed according to the linter. mohor 7712d 14h /can/tags/rel_18/
108 Fixed according to the linter. mohor 7712d 14h /can/tags/rel_18/
107 Fixed according to the linter. mohor 7712d 15h /can/tags/rel_18/
106 Unused signal removed. mohor 7718d 13h /can/tags/rel_18/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7719d 02h /can/tags/rel_18/
102 Little fixes (to fix warnings). mohor 7721d 17h /can/tags/rel_18/
100 Synchronization changed. mohor 7725d 19h /can/tags/rel_18/

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