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[/] [can/] [tags/] [rel_18/] [rtl/] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5571d 19h	/can/tags/rel_18/rtl/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7558d 17h	/can/tags/rel_18/rtl/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7559d 13h	/can/tags/rel_18/rtl/
125	Synchronization changed, error counters fixed.	mohor	7563d 19h	/can/tags/rel_18/rtl/
124	ALTERA_RAM supported.	mohor	7584d 01h	/can/tags/rel_18/rtl/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7591d 07h	/can/tags/rel_18/rtl/
118	Artisan RAM fixed (when not using BIST).	mohor	7600d 04h	/can/tags/rel_18/rtl/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7600d 04h	/can/tags/rel_18/rtl/
115	Artisan ram instances added.	simons	7605d 22h	/can/tags/rel_18/rtl/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7632d 23h	/can/tags/rel_18/rtl/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7634d 23h	/can/tags/rel_18/rtl/
110	Fixed according to the linter.	mohor	7634d 23h	/can/tags/rel_18/rtl/
109	Fixed according to the linter.	mohor	7635d 00h	/can/tags/rel_18/rtl/
108	Fixed according to the linter.	mohor	7635d 01h	/can/tags/rel_18/rtl/
107	Fixed according to the linter.	mohor	7635d 01h	/can/tags/rel_18/rtl/
106	Unused signal removed.	mohor	7640d 23h	/can/tags/rel_18/rtl/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7641d 12h	/can/tags/rel_18/rtl/
102	Little fixes (to fix warnings).	mohor	7644d 03h	/can/tags/rel_18/rtl/
100	Synchronization changed.	mohor	7648d 05h	/can/tags/rel_18/rtl/
99	PCI_BIST replaced with CAN_BIST.	mohor	7648d 05h	/can/tags/rel_18/rtl/

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[/] [can/] [tags/] [rel_18/] [rtl/] - Rev 161

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