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[/] [can/] [tags/] [rel_18/] [sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5571d 16h /can/tags/rel_18/sim/
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7558d 15h /can/tags/rel_18/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7558d 15h /can/tags/rel_18/sim/
119 Artisan RAMs added. mohor 7600d 02h /can/tags/rel_18/sim/
48 Actel APA ram supported. mohor 7771d 13h /can/tags/rel_18/sim/
35 Several registers added. Not finished, yet. mohor 7786d 16h /can/tags/rel_18/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7791d 17h /can/tags/rel_18/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7792d 10h /can/tags/rel_18/sim/
25 *** empty log message *** mohor 7796d 21h /can/tags/rel_18/sim/
24 backup. mohor 7801d 11h /can/tags/rel_18/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7816d 23h /can/tags/rel_18/sim/
16 rx_fifo is now working. mohor 7818d 00h /can/tags/rel_18/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7822d 14h /can/tags/rel_18/sim/
13 Temporary files (backup). mohor 7822d 21h /can/tags/rel_18/sim/
11 Acceptance filter added. mohor 7824d 10h /can/tags/rel_18/sim/
8 Testbench define file added. Clock divider register added. mohor 7836d 20h /can/tags/rel_18/sim/
5 Synchronization working. mohor 7837d 22h /can/tags/rel_18/sim/
4 Dir keeper. mohor 7842d 19h /can/tags/rel_18/sim/
2 Initial mohor 7842d 19h /can/tags/rel_18/sim/

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