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Rev Log message Author Age Path
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7706d 22h /can/tags/rel_20/
102 Little fixes (to fix warnings). mohor 7709d 13h /can/tags/rel_20/
100 Synchronization changed. mohor 7713d 15h /can/tags/rel_20/
99 PCI_BIST replaced with CAN_BIST. mohor 7713d 15h /can/tags/rel_20/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7719d 02h /can/tags/rel_20/
95 Virtual silicon ram instances added. simons 7719d 03h /can/tags/rel_20/
93 synthesis full_case parallel_case fixed. mohor 7724d 14h /can/tags/rel_20/
92 clkout is clk/2 after the reset. mohor 7724d 23h /can/tags/rel_20/
90 paralel_case and full_case compiler directives added to case statements. mohor 7725d 12h /can/tags/rel_20/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7726d 09h /can/tags/rel_20/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7726d 10h /can/tags/rel_20/
85 Typo fixed. mohor 7728d 01h /can/tags/rel_20/
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7729d 08h /can/tags/rel_20/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7729d 09h /can/tags/rel_20/
82 Removed few signals. mohor 7729d 10h /can/tags/rel_20/
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7729d 10h /can/tags/rel_20/
80 Form error was detected when stuff bit occured at the end of crc. mohor 7729d 10h /can/tags/rel_20/
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7730d 10h /can/tags/rel_20/
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7730d 10h /can/tags/rel_20/
77 Synchronization is also needed when transmitting a message. mohor 7733d 09h /can/tags/rel_20/

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