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[/] [can/] [tags/] [rel_20/] - Rev 58

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Rev	Log message	Author	Age	Path
58	timescale.v is used for simulation only.	mohor	7795d 05h	/can/tags/rel_20/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7795d 05h	/can/tags/rel_20/
56	Doubled declarations removed.	mohor	7796d 04h	/can/tags/rel_20/
55	wire declaration added.	mohor	7796d 04h	/can/tags/rel_20/
53	CAN pins located.	mohor	7801d 06h	/can/tags/rel_20/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7801d 06h	/can/tags/rel_20/
51	Xilinx RAM added.	mohor	7801d 07h	/can/tags/rel_20/
50	Top level signal names changed.	mohor	7801d 07h	/can/tags/rel_20/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7804d 22h	/can/tags/rel_20/
48	Actel APA ram supported.	mohor	7804d 23h	/can/tags/rel_20/
47	Data is latched on read.	mohor	7804d 23h	/can/tags/rel_20/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7814d 21h	/can/tags/rel_20/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7814d 22h	/can/tags/rel_20/
43	Directory keeper.	mohor	7815d 05h	/can/tags/rel_20/
42	Initial version of the project.	mohor	7815d 05h	/can/tags/rel_20/
41	Incomplete sensitivity list fixed.	mohor	7815d 06h	/can/tags/rel_20/
40	Typo fixed.	mohor	7815d 06h	/can/tags/rel_20/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7815d 07h	/can/tags/rel_20/
38	Temporary backup version (still fully operable).	mohor	7816d 21h	/can/tags/rel_20/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7816d 21h	/can/tags/rel_20/

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[/] [can/] [tags/] [rel_20/] - Rev 58

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