URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_20/] - Rev 67

Rev	Log message	Author	Age	Path
67	CAN interrupt is active low.	mohor	7780d 10h	/can/tags/rel_20/
66	unix.	mohor	7786d 04h	/can/tags/rel_20/
65	unix.	mohor	7786d 04h	/can/tags/rel_20/
64	* empty log message *	mohor	7786d 04h	/can/tags/rel_20/
63	ALE changes on negedge of clk.	mohor	7792d 02h	/can/tags/rel_20/
62	can_cs signal used for generation of the cs.	mohor	7792d 02h	/can/tags/rel_20/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7794d 15h	/can/tags/rel_20/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7794d 17h	/can/tags/rel_20/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7794d 17h	/can/tags/rel_20/
58	timescale.v is used for simulation only.	mohor	7795d 05h	/can/tags/rel_20/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7795d 05h	/can/tags/rel_20/
56	Doubled declarations removed.	mohor	7796d 04h	/can/tags/rel_20/
55	wire declaration added.	mohor	7796d 04h	/can/tags/rel_20/
53	CAN pins located.	mohor	7801d 06h	/can/tags/rel_20/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7801d 06h	/can/tags/rel_20/
51	Xilinx RAM added.	mohor	7801d 06h	/can/tags/rel_20/
50	Top level signal names changed.	mohor	7801d 06h	/can/tags/rel_20/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7804d 22h	/can/tags/rel_20/
48	Actel APA ram supported.	mohor	7804d 22h	/can/tags/rel_20/
47	Data is latched on read.	mohor	7804d 22h	/can/tags/rel_20/