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[/] [can/] [tags/] [rel_20/] [rtl/] - Rev 141

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Rev	Log message	Author	Age	Path
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7391d 16h	/can/tags/rel_20/rtl/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7485d 18h	/can/tags/rel_20/rtl/
137	Header changed.	mohor	7485d 18h	/can/tags/rel_20/rtl/
136	Error counters changed.	mohor	7485d 18h	/can/tags/rel_20/rtl/
135	Header changed.	mohor	7485d 18h	/can/tags/rel_20/rtl/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7593d 16h	/can/tags/rel_20/rtl/
130	mbist signals updated according to newest convention	markom	7600d 03h	/can/tags/rel_20/rtl/
129	Error counters changed.	mohor	7616d 11h	/can/tags/rel_20/rtl/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7617d 08h	/can/tags/rel_20/rtl/
125	Synchronization changed, error counters fixed.	mohor	7621d 14h	/can/tags/rel_20/rtl/
124	ALTERA_RAM supported.	mohor	7641d 20h	/can/tags/rel_20/rtl/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7649d 01h	/can/tags/rel_20/rtl/
118	Artisan RAM fixed (when not using BIST).	mohor	7657d 22h	/can/tags/rel_20/rtl/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7657d 22h	/can/tags/rel_20/rtl/
115	Artisan ram instances added.	simons	7663d 16h	/can/tags/rel_20/rtl/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7690d 17h	/can/tags/rel_20/rtl/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7692d 17h	/can/tags/rel_20/rtl/
110	Fixed according to the linter.	mohor	7692d 17h	/can/tags/rel_20/rtl/
109	Fixed according to the linter.	mohor	7692d 18h	/can/tags/rel_20/rtl/
108	Fixed according to the linter.	mohor	7692d 19h	/can/tags/rel_20/rtl/

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[/] [can/] [tags/] [rel_20/] [rtl/] - Rev 141

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