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Rev Log message Author Age Path
161 New directory structure. root 5578d 04h /can/tags/rel_20/sim/
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7340d 08h /can/tags/rel_20/sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7340d 08h /can/tags/rel_20/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7565d 03h /can/tags/rel_20/sim/
119 Artisan RAMs added. mohor 7606d 14h /can/tags/rel_20/sim/
48 Actel APA ram supported. mohor 7778d 01h /can/tags/rel_20/sim/
35 Several registers added. Not finished, yet. mohor 7793d 03h /can/tags/rel_20/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7798d 05h /can/tags/rel_20/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7798d 21h /can/tags/rel_20/sim/
25 *** empty log message *** mohor 7803d 09h /can/tags/rel_20/sim/
24 backup. mohor 7807d 22h /can/tags/rel_20/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7823d 10h /can/tags/rel_20/sim/
16 rx_fifo is now working. mohor 7824d 11h /can/tags/rel_20/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7829d 02h /can/tags/rel_20/sim/
13 Temporary files (backup). mohor 7829d 09h /can/tags/rel_20/sim/
11 Acceptance filter added. mohor 7830d 21h /can/tags/rel_20/sim/
8 Testbench define file added. Clock divider register added. mohor 7843d 08h /can/tags/rel_20/sim/
5 Synchronization working. mohor 7844d 09h /can/tags/rel_20/sim/
4 Dir keeper. mohor 7849d 07h /can/tags/rel_20/sim/
2 Initial mohor 7849d 07h /can/tags/rel_20/sim/

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