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[/] [can/] [tags/] [rel_20/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5602d 22h /can/tags/rel_20/sim/rtl_sim/
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7365d 02h /can/tags/rel_20/sim/rtl_sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7365d 02h /can/tags/rel_20/sim/rtl_sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7589d 21h /can/tags/rel_20/sim/rtl_sim/
119 Artisan RAMs added. mohor 7631d 08h /can/tags/rel_20/sim/rtl_sim/
48 Actel APA ram supported. mohor 7802d 19h /can/tags/rel_20/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7817d 21h /can/tags/rel_20/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7822d 23h /can/tags/rel_20/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7823d 15h /can/tags/rel_20/sim/rtl_sim/
25 *** empty log message *** mohor 7828d 03h /can/tags/rel_20/sim/rtl_sim/
24 backup. mohor 7832d 16h /can/tags/rel_20/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7848d 04h /can/tags/rel_20/sim/rtl_sim/
16 rx_fifo is now working. mohor 7849d 05h /can/tags/rel_20/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7853d 20h /can/tags/rel_20/sim/rtl_sim/
13 Temporary files (backup). mohor 7854d 03h /can/tags/rel_20/sim/rtl_sim/
11 Acceptance filter added. mohor 7855d 16h /can/tags/rel_20/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7868d 02h /can/tags/rel_20/sim/rtl_sim/
5 Synchronization working. mohor 7869d 03h /can/tags/rel_20/sim/rtl_sim/
4 Dir keeper. mohor 7874d 01h /can/tags/rel_20/sim/rtl_sim/
2 Initial mohor 7874d 01h /can/tags/rel_20/sim/rtl_sim/

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