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Rev Log message Author Age Path
161 New directory structure. root 5563d 05h /can/tags/rel_21/
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7306d 10h /tags/rel_21/
143 Bit acceptance_filter_mode was inverted. igorm 7306d 10h /trunk/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7325d 08h /trunk/
140 I forgot to thange one signal name. igorm 7380d 07h /trunk/
139 Signal bus_off_on added. igorm 7380d 07h /trunk/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7419d 09h /trunk/
137 Header changed. mohor 7419d 10h /trunk/
136 Error counters changed. mohor 7419d 10h /trunk/
135 Header changed. mohor 7419d 10h /trunk/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7527d 07h /trunk/
130 mbist signals updated according to newest convention markom 7533d 18h /trunk/
129 Error counters changed. mohor 7550d 03h /trunk/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7550d 03h /trunk/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7550d 23h /trunk/
125 Synchronization changed, error counters fixed. mohor 7555d 05h /trunk/
124 ALTERA_RAM supported. mohor 7575d 12h /trunk/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7582d 17h /trunk/
119 Artisan RAMs added. mohor 7591d 14h /trunk/
118 Artisan RAM fixed (when not using BIST). mohor 7591d 14h /trunk/

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