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[/] [can/] [tags/] [rel_21/] [rtl/] [verilog/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5571d 17h /can/tags/rel_21/rtl/verilog/
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7314d 22h /can/tags/rel_21/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7314d 22h /can/tags/rel_21/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7333d 21h /can/tags/rel_21/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7427d 22h /can/tags/rel_21/rtl/verilog/
137 Header changed. mohor 7427d 22h /can/tags/rel_21/rtl/verilog/
136 Error counters changed. mohor 7427d 23h /can/tags/rel_21/rtl/verilog/
135 Header changed. mohor 7427d 23h /can/tags/rel_21/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7535d 20h /can/tags/rel_21/rtl/verilog/
130 mbist signals updated according to newest convention markom 7542d 07h /can/tags/rel_21/rtl/verilog/
129 Error counters changed. mohor 7558d 16h /can/tags/rel_21/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7559d 12h /can/tags/rel_21/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7563d 18h /can/tags/rel_21/rtl/verilog/
124 ALTERA_RAM supported. mohor 7584d 00h /can/tags/rel_21/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7591d 06h /can/tags/rel_21/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7600d 03h /can/tags/rel_21/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7600d 03h /can/tags/rel_21/rtl/verilog/
115 Artisan ram instances added. simons 7605d 21h /can/tags/rel_21/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7632d 22h /can/tags/rel_21/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7634d 22h /can/tags/rel_21/rtl/verilog/

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