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Rev Log message Author Age Path
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7684d 08h /can/tags/rel_22/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7686d 08h /can/tags/rel_22/
110 Fixed according to the linter. mohor 7686d 08h /can/tags/rel_22/
109 Fixed according to the linter. mohor 7686d 09h /can/tags/rel_22/
108 Fixed according to the linter. mohor 7686d 10h /can/tags/rel_22/
107 Fixed according to the linter. mohor 7686d 10h /can/tags/rel_22/
106 Unused signal removed. mohor 7692d 08h /can/tags/rel_22/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7692d 21h /can/tags/rel_22/
102 Little fixes (to fix warnings). mohor 7695d 12h /can/tags/rel_22/
100 Synchronization changed. mohor 7699d 14h /can/tags/rel_22/
99 PCI_BIST replaced with CAN_BIST. mohor 7699d 14h /can/tags/rel_22/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7705d 01h /can/tags/rel_22/
95 Virtual silicon ram instances added. simons 7705d 02h /can/tags/rel_22/
93 synthesis full_case parallel_case fixed. mohor 7710d 13h /can/tags/rel_22/
92 clkout is clk/2 after the reset. mohor 7710d 22h /can/tags/rel_22/
90 paralel_case and full_case compiler directives added to case statements. mohor 7711d 11h /can/tags/rel_22/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7712d 08h /can/tags/rel_22/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7712d 09h /can/tags/rel_22/
85 Typo fixed. mohor 7714d 00h /can/tags/rel_22/
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7715d 07h /can/tags/rel_22/

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