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Rev Log message Author Age Path
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7648d 10h /can/tags/rel_22/
125 Synchronization changed, error counters fixed. mohor 7652d 16h /can/tags/rel_22/
124 ALTERA_RAM supported. mohor 7672d 22h /can/tags/rel_22/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7680d 04h /can/tags/rel_22/
119 Artisan RAMs added. mohor 7689d 01h /can/tags/rel_22/
118 Artisan RAM fixed (when not using BIST). mohor 7689d 01h /can/tags/rel_22/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7689d 01h /can/tags/rel_22/
115 Artisan ram instances added. simons 7694d 19h /can/tags/rel_22/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7721d 19h /can/tags/rel_22/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7723d 19h /can/tags/rel_22/
110 Fixed according to the linter. mohor 7723d 20h /can/tags/rel_22/
109 Fixed according to the linter. mohor 7723d 21h /can/tags/rel_22/
108 Fixed according to the linter. mohor 7723d 21h /can/tags/rel_22/
107 Fixed according to the linter. mohor 7723d 21h /can/tags/rel_22/
106 Unused signal removed. mohor 7729d 19h /can/tags/rel_22/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7730d 09h /can/tags/rel_22/
102 Little fixes (to fix warnings). mohor 7732d 23h /can/tags/rel_22/
100 Synchronization changed. mohor 7737d 01h /can/tags/rel_22/
99 PCI_BIST replaced with CAN_BIST. mohor 7737d 01h /can/tags/rel_22/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7742d 12h /can/tags/rel_22/

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