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[/] [can/] [tags/] [rel_22/] [rtl/] - Rev 124

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Rev	Log message	Author	Age	Path
124	ALTERA_RAM supported.	mohor	7601d 18h	/can/tags/rel_22/rtl/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7608d 23h	/can/tags/rel_22/rtl/
118	Artisan RAM fixed (when not using BIST).	mohor	7617d 20h	/can/tags/rel_22/rtl/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7617d 20h	/can/tags/rel_22/rtl/
115	Artisan ram instances added.	simons	7623d 14h	/can/tags/rel_22/rtl/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7650d 15h	/can/tags/rel_22/rtl/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7652d 15h	/can/tags/rel_22/rtl/
110	Fixed according to the linter.	mohor	7652d 15h	/can/tags/rel_22/rtl/
109	Fixed according to the linter.	mohor	7652d 16h	/can/tags/rel_22/rtl/
108	Fixed according to the linter.	mohor	7652d 17h	/can/tags/rel_22/rtl/
107	Fixed according to the linter.	mohor	7652d 17h	/can/tags/rel_22/rtl/
106	Unused signal removed.	mohor	7658d 15h	/can/tags/rel_22/rtl/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7659d 04h	/can/tags/rel_22/rtl/
102	Little fixes (to fix warnings).	mohor	7661d 19h	/can/tags/rel_22/rtl/
100	Synchronization changed.	mohor	7665d 21h	/can/tags/rel_22/rtl/
99	PCI_BIST replaced with CAN_BIST.	mohor	7665d 21h	/can/tags/rel_22/rtl/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7671d 08h	/can/tags/rel_22/rtl/
95	Virtual silicon ram instances added.	simons	7671d 09h	/can/tags/rel_22/rtl/
93	synthesis full_case parallel_case fixed.	mohor	7676d 21h	/can/tags/rel_22/rtl/
92	clkout is clk/2 after the reset.	mohor	7677d 05h	/can/tags/rel_22/rtl/

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[/] [can/] [tags/] [rel_22/] [rtl/] - Rev 124

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