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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] - Rev 57

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Rev	Log message	Author	Age	Path
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7827d 23h	/can/tags/rel_22/rtl/verilog/
56	Doubled declarations removed.	mohor	7828d 22h	/can/tags/rel_22/rtl/verilog/
55	wire declaration added.	mohor	7828d 22h	/can/tags/rel_22/rtl/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7834d 00h	/can/tags/rel_22/rtl/verilog/
51	Xilinx RAM added.	mohor	7834d 00h	/can/tags/rel_22/rtl/verilog/
50	Top level signal names changed.	mohor	7834d 00h	/can/tags/rel_22/rtl/verilog/
48	Actel APA ram supported.	mohor	7837d 16h	/can/tags/rel_22/rtl/verilog/
47	Data is latched on read.	mohor	7837d 16h	/can/tags/rel_22/rtl/verilog/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7847d 15h	/can/tags/rel_22/rtl/verilog/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7847d 16h	/can/tags/rel_22/rtl/verilog/
41	Incomplete sensitivity list fixed.	mohor	7848d 00h	/can/tags/rel_22/rtl/verilog/
40	Typo fixed.	mohor	7848d 00h	/can/tags/rel_22/rtl/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7848d 00h	/can/tags/rel_22/rtl/verilog/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7849d 15h	/can/tags/rel_22/rtl/verilog/
35	Several registers added. Not finished, yet.	mohor	7852d 19h	/can/tags/rel_22/rtl/verilog/
33	abort_tx added.	mohor	7855d 01h	/can/tags/rel_22/rtl/verilog/
32	abort_tx added. Bit destuff fixed.	mohor	7855d 01h	/can/tags/rel_22/rtl/verilog/
31	Wishbone interface added.	mohor	7856d 14h	/can/tags/rel_22/rtl/verilog/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7856d 23h	/can/tags/rel_22/rtl/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7857d 20h	/can/tags/rel_22/rtl/verilog/

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] - Rev 57

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