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Rev Log message Author Age Path
161 New directory structure. root 5675d 08h /can/tags/rel_22/sim/
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7271d 21h /can/tags/rel_22/sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7437d 12h /can/tags/rel_22/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7662d 07h /can/tags/rel_22/sim/
119 Artisan RAMs added. mohor 7703d 18h /can/tags/rel_22/sim/
48 Actel APA ram supported. mohor 7875d 05h /can/tags/rel_22/sim/
35 Several registers added. Not finished, yet. mohor 7890d 07h /can/tags/rel_22/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7895d 09h /can/tags/rel_22/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7896d 01h /can/tags/rel_22/sim/
25 *** empty log message *** mohor 7900d 13h /can/tags/rel_22/sim/
24 backup. mohor 7905d 02h /can/tags/rel_22/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7920d 14h /can/tags/rel_22/sim/
16 rx_fifo is now working. mohor 7921d 15h /can/tags/rel_22/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7926d 06h /can/tags/rel_22/sim/
13 Temporary files (backup). mohor 7926d 13h /can/tags/rel_22/sim/
11 Acceptance filter added. mohor 7928d 01h /can/tags/rel_22/sim/
8 Testbench define file added. Clock divider register added. mohor 7940d 12h /can/tags/rel_22/sim/
5 Synchronization working. mohor 7941d 13h /can/tags/rel_22/sim/
4 Dir keeper. mohor 7946d 11h /can/tags/rel_22/sim/
2 Initial mohor 7946d 11h /can/tags/rel_22/sim/

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