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[/] [can/] [tags/] [rel_22/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5637d 08h /can/tags/rel_22/sim/rtl_sim/
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7233d 21h /can/tags/rel_22/sim/rtl_sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7399d 12h /can/tags/rel_22/sim/rtl_sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7624d 07h /can/tags/rel_22/sim/rtl_sim/
119 Artisan RAMs added. mohor 7665d 18h /can/tags/rel_22/sim/rtl_sim/
48 Actel APA ram supported. mohor 7837d 05h /can/tags/rel_22/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7852d 08h /can/tags/rel_22/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7857d 09h /can/tags/rel_22/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7858d 02h /can/tags/rel_22/sim/rtl_sim/
25 *** empty log message *** mohor 7862d 13h /can/tags/rel_22/sim/rtl_sim/
24 backup. mohor 7867d 03h /can/tags/rel_22/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7882d 15h /can/tags/rel_22/sim/rtl_sim/
16 rx_fifo is now working. mohor 7883d 16h /can/tags/rel_22/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7888d 06h /can/tags/rel_22/sim/rtl_sim/
13 Temporary files (backup). mohor 7888d 13h /can/tags/rel_22/sim/rtl_sim/
11 Acceptance filter added. mohor 7890d 02h /can/tags/rel_22/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7902d 12h /can/tags/rel_22/sim/rtl_sim/
5 Synchronization working. mohor 7903d 14h /can/tags/rel_22/sim/rtl_sim/
4 Dir keeper. mohor 7908d 11h /can/tags/rel_22/sim/rtl_sim/
2 Initial mohor 7908d 11h /can/tags/rel_22/sim/rtl_sim/

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