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[/] [can/] [tags/] [rel_23/] [bench/] [verilog/] - Rev 127

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Rev Log message Author Age Path
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7624d 13h /can/tags/rel_23/bench/verilog/
119 Artisan RAMs added. mohor 7665d 23h /can/tags/rel_23/bench/verilog/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7729d 18h /can/tags/rel_23/bench/verilog/
68 CAN inturrupt is active low. mohor 7812d 22h /can/tags/rel_23/bench/verilog/
63 ALE changes on negedge of clk. mohor 7824d 14h /can/tags/rel_23/bench/verilog/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7827d 03h /can/tags/rel_23/bench/verilog/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7827d 05h /can/tags/rel_23/bench/verilog/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7827d 05h /can/tags/rel_23/bench/verilog/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7833d 18h /can/tags/rel_23/bench/verilog/
50 Top level signal names changed. mohor 7833d 18h /can/tags/rel_23/bench/verilog/
48 Actel APA ram supported. mohor 7837d 10h /can/tags/rel_23/bench/verilog/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7847d 19h /can/tags/rel_23/bench/verilog/
38 Temporary backup version (still fully operable). mohor 7849d 09h /can/tags/rel_23/bench/verilog/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7849d 09h /can/tags/rel_23/bench/verilog/
35 Several registers added. Not finished, yet. mohor 7852d 13h /can/tags/rel_23/bench/verilog/
34 Errors monitoring improved. arbitration_lost improved. mohor 7854d 19h /can/tags/rel_23/bench/verilog/
31 Wishbone interface added. mohor 7856d 08h /can/tags/rel_23/bench/verilog/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7857d 15h /can/tags/rel_23/bench/verilog/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7858d 07h /can/tags/rel_23/bench/verilog/
26 Backup. mohor 7862d 16h /can/tags/rel_23/bench/verilog/

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