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147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7233d 18h /can/tags/rel_23/rtl/verilog/
145 Arbitration bug fixed. igorm 7233d 23h /can/tags/rel_23/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7380d 15h /can/tags/rel_23/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7399d 13h /can/tags/rel_23/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7493d 15h /can/tags/rel_23/rtl/verilog/
137 Header changed. mohor 7493d 15h /can/tags/rel_23/rtl/verilog/
136 Error counters changed. mohor 7493d 15h /can/tags/rel_23/rtl/verilog/
135 Header changed. mohor 7493d 15h /can/tags/rel_23/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7601d 13h /can/tags/rel_23/rtl/verilog/
130 mbist signals updated according to newest convention markom 7608d 00h /can/tags/rel_23/rtl/verilog/
129 Error counters changed. mohor 7624d 08h /can/tags/rel_23/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7625d 05h /can/tags/rel_23/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7629d 11h /can/tags/rel_23/rtl/verilog/
124 ALTERA_RAM supported. mohor 7649d 17h /can/tags/rel_23/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7656d 22h /can/tags/rel_23/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7665d 19h /can/tags/rel_23/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7665d 20h /can/tags/rel_23/rtl/verilog/
115 Artisan ram instances added. simons 7671d 13h /can/tags/rel_23/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7698d 14h /can/tags/rel_23/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7700d 14h /can/tags/rel_23/rtl/verilog/

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