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Rev Log message Author Age Path
161 New directory structure. root 5607d 20h /can/tags/rel_23/sim/
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7204d 04h /can/tags/rel_23/sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7370d 00h /can/tags/rel_23/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7594d 19h /can/tags/rel_23/sim/
119 Artisan RAMs added. mohor 7636d 06h /can/tags/rel_23/sim/
48 Actel APA ram supported. mohor 7807d 17h /can/tags/rel_23/sim/
35 Several registers added. Not finished, yet. mohor 7822d 20h /can/tags/rel_23/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 7827d 21h /can/tags/rel_23/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.
mohor 7828d 14h /can/tags/rel_23/sim/
25 *** empty log message *** mohor 7833d 02h /can/tags/rel_23/sim/
24 backup. mohor 7837d 15h /can/tags/rel_23/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7853d 03h /can/tags/rel_23/sim/
16 rx_fifo is now working. mohor 7854d 04h /can/tags/rel_23/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7858d 18h /can/tags/rel_23/sim/
13 Temporary files (backup). mohor 7859d 01h /can/tags/rel_23/sim/
11 Acceptance filter added. mohor 7860d 14h /can/tags/rel_23/sim/
8 Testbench define file added. Clock divider register added. mohor 7873d 00h /can/tags/rel_23/sim/
5 Synchronization working. mohor 7874d 02h /can/tags/rel_23/sim/
4 Dir keeper. mohor 7878d 23h /can/tags/rel_23/sim/
2 Initial mohor 7878d 23h /can/tags/rel_23/sim/

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