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[/] [can/] [tags/] [rel_23/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5599d 16h /can/tags/rel_23/sim/rtl_sim/
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7196d 00h /can/tags/rel_23/sim/rtl_sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7361d 20h /can/tags/rel_23/sim/rtl_sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7586d 15h /can/tags/rel_23/sim/rtl_sim/
119 Artisan RAMs added. mohor 7628d 02h /can/tags/rel_23/sim/rtl_sim/
48 Actel APA ram supported. mohor 7799d 13h /can/tags/rel_23/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7814d 16h /can/tags/rel_23/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7819d 17h /can/tags/rel_23/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7820d 10h /can/tags/rel_23/sim/rtl_sim/
25 *** empty log message *** mohor 7824d 21h /can/tags/rel_23/sim/rtl_sim/
24 backup. mohor 7829d 11h /can/tags/rel_23/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7844d 23h /can/tags/rel_23/sim/rtl_sim/
16 rx_fifo is now working. mohor 7846d 00h /can/tags/rel_23/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7850d 14h /can/tags/rel_23/sim/rtl_sim/
13 Temporary files (backup). mohor 7850d 21h /can/tags/rel_23/sim/rtl_sim/
11 Acceptance filter added. mohor 7852d 10h /can/tags/rel_23/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7864d 20h /can/tags/rel_23/sim/rtl_sim/
5 Synchronization working. mohor 7865d 22h /can/tags/rel_23/sim/rtl_sim/
4 Dir keeper. mohor 7870d 19h /can/tags/rel_23/sim/rtl_sim/
2 Initial mohor 7870d 19h /can/tags/rel_23/sim/rtl_sim/

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