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Rev Log message Author Age Path
129 Error counters changed. mohor 7586d 19h /can/tags/rel_24/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7586d 19h /can/tags/rel_24/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7587d 15h /can/tags/rel_24/
125 Synchronization changed, error counters fixed. mohor 7591d 21h /can/tags/rel_24/
124 ALTERA_RAM supported. mohor 7612d 03h /can/tags/rel_24/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7619d 09h /can/tags/rel_24/
119 Artisan RAMs added. mohor 7628d 06h /can/tags/rel_24/
118 Artisan RAM fixed (when not using BIST). mohor 7628d 06h /can/tags/rel_24/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7628d 06h /can/tags/rel_24/
115 Artisan ram instances added. simons 7634d 00h /can/tags/rel_24/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7661d 00h /can/tags/rel_24/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7663d 01h /can/tags/rel_24/
110 Fixed according to the linter. mohor 7663d 01h /can/tags/rel_24/
109 Fixed according to the linter. mohor 7663d 02h /can/tags/rel_24/
108 Fixed according to the linter. mohor 7663d 02h /can/tags/rel_24/
107 Fixed according to the linter. mohor 7663d 03h /can/tags/rel_24/
106 Unused signal removed. mohor 7669d 00h /can/tags/rel_24/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7669d 14h /can/tags/rel_24/
102 Little fixes (to fix warnings). mohor 7672d 05h /can/tags/rel_24/
100 Synchronization changed. mohor 7676d 06h /can/tags/rel_24/

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