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Rev Log message Author Age Path
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7464d 00h /can/tags/rel_24/
137 Header changed. mohor 7464d 00h /can/tags/rel_24/
136 Error counters changed. mohor 7464d 01h /can/tags/rel_24/
135 Header changed. mohor 7464d 01h /can/tags/rel_24/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7571d 22h /can/tags/rel_24/
130 mbist signals updated according to newest convention markom 7578d 09h /can/tags/rel_24/
129 Error counters changed. mohor 7594d 18h /can/tags/rel_24/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7594d 18h /can/tags/rel_24/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7595d 14h /can/tags/rel_24/
125 Synchronization changed, error counters fixed. mohor 7599d 20h /can/tags/rel_24/
124 ALTERA_RAM supported. mohor 7620d 02h /can/tags/rel_24/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7627d 08h /can/tags/rel_24/
119 Artisan RAMs added. mohor 7636d 05h /can/tags/rel_24/
118 Artisan RAM fixed (when not using BIST). mohor 7636d 05h /can/tags/rel_24/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7636d 05h /can/tags/rel_24/
115 Artisan ram instances added. simons 7641d 23h /can/tags/rel_24/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7669d 00h /can/tags/rel_24/
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7671d 00h /can/tags/rel_24/
110 Fixed according to the linter. mohor 7671d 00h /can/tags/rel_24/
109 Fixed according to the linter. mohor 7671d 01h /can/tags/rel_24/

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