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Rev	Log message	Author	Age	Path
150	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7202d 02h	/can/tags/rel_24/bench/verilog/
140	I forgot to thange one signal name.	igorm	7425d 03h	/can/tags/rel_24/bench/verilog/
139	Signal bus_off_on added.	igorm	7425d 04h	/can/tags/rel_24/bench/verilog/
130	mbist signals updated according to newest convention	markom	7578d 15h	/can/tags/rel_24/bench/verilog/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7595d 00h	/can/tags/rel_24/bench/verilog/
119	Artisan RAMs added.	mohor	7636d 11h	/can/tags/rel_24/bench/verilog/
83	cs_can_i is used only when WISHBONE interface is not used.	mohor	7700d 06h	/can/tags/rel_24/bench/verilog/
68	CAN inturrupt is active low.	mohor	7783d 10h	/can/tags/rel_24/bench/verilog/
63	ALE changes on negedge of clk.	mohor	7795d 01h	/can/tags/rel_24/bench/verilog/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7797d 15h	/can/tags/rel_24/bench/verilog/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7797d 16h	/can/tags/rel_24/bench/verilog/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 17h	/can/tags/rel_24/bench/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 06h	/can/tags/rel_24/bench/verilog/
50	Top level signal names changed.	mohor	7804d 06h	/can/tags/rel_24/bench/verilog/
48	Actel APA ram supported.	mohor	7807d 22h	/can/tags/rel_24/bench/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7818d 06h	/can/tags/rel_24/bench/verilog/
38	Temporary backup version (still fully operable).	mohor	7819d 21h	/can/tags/rel_24/bench/verilog/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7819d 21h	/can/tags/rel_24/bench/verilog/
35	Several registers added. Not finished, yet.	mohor	7823d 01h	/can/tags/rel_24/bench/verilog/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7825d 07h	/can/tags/rel_24/bench/verilog/

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