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Rev Log message Author Age Path
161 New directory structure. root 5623d 02h /can/tags/rel_24/rtl/verilog/
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7217d 03h /can/tags/rel_24/rtl/verilog/
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7217d 03h /can/tags/rel_24/rtl/verilog/
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7219d 10h /can/tags/rel_24/rtl/verilog/
145 Arbitration bug fixed. igorm 7219d 15h /can/tags/rel_24/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7366d 07h /can/tags/rel_24/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7385d 06h /can/tags/rel_24/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7479d 07h /can/tags/rel_24/rtl/verilog/
137 Header changed. mohor 7479d 07h /can/tags/rel_24/rtl/verilog/
136 Error counters changed. mohor 7479d 08h /can/tags/rel_24/rtl/verilog/
135 Header changed. mohor 7479d 08h /can/tags/rel_24/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7587d 05h /can/tags/rel_24/rtl/verilog/
130 mbist signals updated according to newest convention markom 7593d 16h /can/tags/rel_24/rtl/verilog/
129 Error counters changed. mohor 7610d 01h /can/tags/rel_24/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7610d 21h /can/tags/rel_24/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7615d 03h /can/tags/rel_24/rtl/verilog/
124 ALTERA_RAM supported. mohor 7635d 09h /can/tags/rel_24/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7642d 15h /can/tags/rel_24/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7651d 12h /can/tags/rel_24/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7651d 12h /can/tags/rel_24/rtl/verilog/

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