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150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7231d 05h /can/tags/rel_24/sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7399d 08h /can/tags/rel_24/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7624d 03h /can/tags/rel_24/sim/
119 Artisan RAMs added. mohor 7665d 14h /can/tags/rel_24/sim/
48 Actel APA ram supported. mohor 7837d 01h /can/tags/rel_24/sim/
35 Several registers added. Not finished, yet. mohor 7852d 03h /can/tags/rel_24/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7857d 05h /can/tags/rel_24/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7857d 21h /can/tags/rel_24/sim/
25 *** empty log message *** mohor 7862d 09h /can/tags/rel_24/sim/
24 backup. mohor 7866d 23h /can/tags/rel_24/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7882d 10h /can/tags/rel_24/sim/
16 rx_fifo is now working. mohor 7883d 11h /can/tags/rel_24/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7888d 02h /can/tags/rel_24/sim/
13 Temporary files (backup). mohor 7888d 09h /can/tags/rel_24/sim/
11 Acceptance filter added. mohor 7889d 22h /can/tags/rel_24/sim/
8 Testbench define file added. Clock divider register added. mohor 7902d 08h /can/tags/rel_24/sim/
5 Synchronization working. mohor 7903d 09h /can/tags/rel_24/sim/
4 Dir keeper. mohor 7908d 07h /can/tags/rel_24/sim/
2 Initial mohor 7908d 07h /can/tags/rel_24/sim/

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