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Rev Log message Author Age Path
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7231d 17h /can/tags/rel_24/sim/rtl_sim/run/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7399d 20h /can/tags/rel_24/sim/rtl_sim/run/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7624d 15h /can/tags/rel_24/sim/rtl_sim/run/
119 Artisan RAMs added. mohor 7666d 02h /can/tags/rel_24/sim/rtl_sim/run/
48 Actel APA ram supported. mohor 7837d 13h /can/tags/rel_24/sim/rtl_sim/run/
35 Several registers added. Not finished, yet. mohor 7852d 16h /can/tags/rel_24/sim/rtl_sim/run/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7857d 18h /can/tags/rel_24/sim/rtl_sim/run/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7858d 10h /can/tags/rel_24/sim/rtl_sim/run/
25 *** empty log message *** mohor 7862d 22h /can/tags/rel_24/sim/rtl_sim/run/
24 backup. mohor 7867d 11h /can/tags/rel_24/sim/rtl_sim/run/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7882d 23h /can/tags/rel_24/sim/rtl_sim/run/
16 rx_fifo is now working. mohor 7884d 00h /can/tags/rel_24/sim/rtl_sim/run/
14 rx fifo added. Not 100 % verified, yet. mohor 7888d 14h /can/tags/rel_24/sim/rtl_sim/run/
13 Temporary files (backup). mohor 7888d 22h /can/tags/rel_24/sim/rtl_sim/run/
11 Acceptance filter added. mohor 7890d 10h /can/tags/rel_24/sim/rtl_sim/run/
8 Testbench define file added. Clock divider register added. mohor 7902d 20h /can/tags/rel_24/sim/rtl_sim/run/
5 Synchronization working. mohor 7903d 22h /can/tags/rel_24/sim/rtl_sim/run/
2 Initial mohor 7908d 20h /can/tags/rel_24/sim/rtl_sim/run/

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