OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_4/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 Xilinx RAM added. mohor 7793d 08h /can/tags/rel_4/
50 Top level signal names changed. mohor 7793d 08h /can/tags/rel_4/
49 Actel APA ram changed. Now synchronous read is used. mohor 7797d 00h /can/tags/rel_4/
48 Actel APA ram supported. mohor 7797d 00h /can/tags/rel_4/
47 Data is latched on read. mohor 7797d 00h /can/tags/rel_4/
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7806d 22h /can/tags/rel_4/
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7807d 00h /can/tags/rel_4/
43 Directory keeper. mohor 7807d 06h /can/tags/rel_4/
42 Initial version of the project. mohor 7807d 06h /can/tags/rel_4/
41 Incomplete sensitivity list fixed. mohor 7807d 08h /can/tags/rel_4/
40 Typo fixed. mohor 7807d 08h /can/tags/rel_4/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7807d 08h /can/tags/rel_4/
38 Temporary backup version (still fully operable). mohor 7808d 23h /can/tags/rel_4/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7808d 23h /can/tags/rel_4/
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 7808d 23h /can/tags/rel_4/
35 Several registers added. Not finished, yet. mohor 7812d 03h /can/tags/rel_4/
34 Errors monitoring improved. arbitration_lost improved. mohor 7814d 08h /can/tags/rel_4/
33 abort_tx added. mohor 7814d 08h /can/tags/rel_4/
32 abort_tx added. Bit destuff fixed. mohor 7814d 09h /can/tags/rel_4/
31 Wishbone interface added. mohor 7815d 22h /can/tags/rel_4/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.