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[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 45

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Rev	Log message	Author	Age	Path
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7847d 09h	/can/tags/rel_6/rtl/verilog/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7847d 10h	/can/tags/rel_6/rtl/verilog/
41	Incomplete sensitivity list fixed.	mohor	7847d 18h	/can/tags/rel_6/rtl/verilog/
40	Typo fixed.	mohor	7847d 18h	/can/tags/rel_6/rtl/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7847d 19h	/can/tags/rel_6/rtl/verilog/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7849d 09h	/can/tags/rel_6/rtl/verilog/
35	Several registers added. Not finished, yet.	mohor	7852d 13h	/can/tags/rel_6/rtl/verilog/
33	abort_tx added.	mohor	7854d 19h	/can/tags/rel_6/rtl/verilog/
32	abort_tx added. Bit destuff fixed.	mohor	7854d 19h	/can/tags/rel_6/rtl/verilog/
31	Wishbone interface added.	mohor	7856d 08h	/can/tags/rel_6/rtl/verilog/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7856d 17h	/can/tags/rel_6/rtl/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7857d 15h	/can/tags/rel_6/rtl/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 07h	/can/tags/rel_6/rtl/verilog/
27	This file is not used.	mohor	7862d 16h	/can/tags/rel_6/rtl/verilog/
26	Backup.	mohor	7862d 16h	/can/tags/rel_6/rtl/verilog/
25	* empty log message *	mohor	7862d 19h	/can/tags/rel_6/rtl/verilog/
24	backup.	mohor	7867d 08h	/can/tags/rel_6/rtl/verilog/
23	Fifo corrected to be synthesizable.	mohor	7880d 16h	/can/tags/rel_6/rtl/verilog/
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7881d 20h	/can/tags/rel_6/rtl/verilog/
21	Data is stored to fifo at the end of ack stage.	mohor	7882d 11h	/can/tags/rel_6/rtl/verilog/

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