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[/] [can/] [tags/] [rel_7/] - Rev 65

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Rev Log message Author Age Path
65 unix. mohor 7771d 23h /can/tags/rel_7/
64 *** empty log message *** mohor 7771d 23h /can/tags/rel_7/
63 ALE changes on negedge of clk. mohor 7777d 20h /can/tags/rel_7/
62 can_cs signal used for generation of the cs. mohor 7777d 20h /can/tags/rel_7/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7780d 10h /can/tags/rel_7/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7780d 11h /can/tags/rel_7/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7780d 12h /can/tags/rel_7/
58 timescale.v is used for simulation only. mohor 7781d 00h /can/tags/rel_7/
57 Mux used for clkout to avoid "gated clocks warning". mohor 7781d 00h /can/tags/rel_7/
56 Doubled declarations removed. mohor 7781d 23h /can/tags/rel_7/
55 wire declaration added. mohor 7781d 23h /can/tags/rel_7/
53 CAN pins located. mohor 7787d 00h /can/tags/rel_7/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7787d 01h /can/tags/rel_7/
51 Xilinx RAM added. mohor 7787d 01h /can/tags/rel_7/
50 Top level signal names changed. mohor 7787d 01h /can/tags/rel_7/
49 Actel APA ram changed. Now synchronous read is used. mohor 7790d 17h /can/tags/rel_7/
48 Actel APA ram supported. mohor 7790d 17h /can/tags/rel_7/
47 Data is latched on read. mohor 7790d 17h /can/tags/rel_7/
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7800d 16h /can/tags/rel_7/
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7800d 17h /can/tags/rel_7/

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