OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 17

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 Addresses corrected to decimal values (previously hex). mohor 7838d 12h /can/tags/rel_7/rtl/verilog/
16 rx_fifo is now working. mohor 7838d 17h /can/tags/rel_7/rtl/verilog/
15 Temporary version (backup). mohor 7842d 11h /can/tags/rel_7/rtl/verilog/
14 rx fifo added. Not 100 % verified, yet. mohor 7843d 07h /can/tags/rel_7/rtl/verilog/
13 Temporary files (backup). mohor 7843d 14h /can/tags/rel_7/rtl/verilog/
12 Temp version. mohor 7844d 15h /can/tags/rel_7/rtl/verilog/
11 Acceptance filter added. mohor 7845d 03h /can/tags/rel_7/rtl/verilog/
10 Backup version. mohor 7856d 01h /can/tags/rel_7/rtl/verilog/
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7857d 05h /can/tags/rel_7/rtl/verilog/
8 Testbench define file added. Clock divider register added. mohor 7857d 13h /can/tags/rel_7/rtl/verilog/
7 Tripple sampling supported. mohor 7858d 03h /can/tags/rel_7/rtl/verilog/
6 Commented lines removed. mohor 7858d 05h /can/tags/rel_7/rtl/verilog/
5 Synchronization working. mohor 7858d 15h /can/tags/rel_7/rtl/verilog/
2 Initial mohor 7863d 12h /can/tags/rel_7/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.