| Rev |
Log message |
Author |
Age |
Path |
| 39 |
CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished. |
mohor |
7820d 02h |
/can/tags/rel_7/rtl/verilog/ |
| 36 |
Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added. |
mohor |
7821d 17h |
/can/tags/rel_7/rtl/verilog/ |
| 35 |
Several registers added. Not finished, yet. |
mohor |
7824d 21h |
/can/tags/rel_7/rtl/verilog/ |
| 33 |
abort_tx added. |
mohor |
7827d 02h |
/can/tags/rel_7/rtl/verilog/ |
| 32 |
abort_tx added. Bit destuff fixed. |
mohor |
7827d 02h |
/can/tags/rel_7/rtl/verilog/ |
| 31 |
Wishbone interface added. |
mohor |
7828d 16h |
/can/tags/rel_7/rtl/verilog/ |
| 30 |
CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added. |
mohor |
7829d 01h |
/can/tags/rel_7/rtl/verilog/ |
| 29 |
Overload fixed. Hard synchronization also enabled at the last bit of
interframe. |
mohor |
7829d 22h |
/can/tags/rel_7/rtl/verilog/ |
| 28 |
Bosch license warning added. Error counters finished. Overload frames
still need to be fixed. |
mohor |
7830d 14h |
/can/tags/rel_7/rtl/verilog/ |
| 27 |
This file is not used. |
mohor |
7834d 23h |
/can/tags/rel_7/rtl/verilog/ |
| 26 |
Backup. |
mohor |
7834d 23h |
/can/tags/rel_7/rtl/verilog/ |
| 25 |
*** empty log message *** |
mohor |
7835d 02h |
/can/tags/rel_7/rtl/verilog/ |
| 24 |
backup. |
mohor |
7839d 16h |
/can/tags/rel_7/rtl/verilog/ |
| 23 |
Fifo corrected to be synthesizable. |
mohor |
7852d 23h |
/can/tags/rel_7/rtl/verilog/ |
| 22 |
Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57). |
mohor |
7854d 03h |
/can/tags/rel_7/rtl/verilog/ |
| 21 |
Data is stored to fifo at the end of ack stage. |
mohor |
7854d 19h |
/can/tags/rel_7/rtl/verilog/ |
| 20 |
CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). |
mohor |
7854d 20h |
/can/tags/rel_7/rtl/verilog/ |
| 19 |
RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. |
mohor |
7855d 02h |
/can/tags/rel_7/rtl/verilog/ |
| 18 |
When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. |
mohor |
7855d 04h |
/can/tags/rel_7/rtl/verilog/ |
| 17 |
Addresses corrected to decimal values (previously hex). |
mohor |
7855d 23h |
/can/tags/rel_7/rtl/verilog/ |
