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[/] [can/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 44

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Rev Log message Author Age Path
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7801d 23h /can/tags/rel_7/rtl/verilog/
41 Incomplete sensitivity list fixed. mohor 7802d 08h /can/tags/rel_7/rtl/verilog/
40 Typo fixed. mohor 7802d 08h /can/tags/rel_7/rtl/verilog/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7802d 08h /can/tags/rel_7/rtl/verilog/
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7803d 23h /can/tags/rel_7/rtl/verilog/
35 Several registers added. Not finished, yet. mohor 7807d 03h /can/tags/rel_7/rtl/verilog/
33 abort_tx added. mohor 7809d 08h /can/tags/rel_7/rtl/verilog/
32 abort_tx added. Bit destuff fixed. mohor 7809d 08h /can/tags/rel_7/rtl/verilog/
31 Wishbone interface added. mohor 7810d 22h /can/tags/rel_7/rtl/verilog/
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.		 mohor 7811d 07h /can/tags/rel_7/rtl/verilog/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7812d 04h /can/tags/rel_7/rtl/verilog/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7812d 20h /can/tags/rel_7/rtl/verilog/
27 This file is not used. mohor 7817d 05h /can/tags/rel_7/rtl/verilog/
26 Backup. mohor 7817d 05h /can/tags/rel_7/rtl/verilog/
25 *** empty log message *** mohor 7817d 08h /can/tags/rel_7/rtl/verilog/
24 backup. mohor 7821d 22h /can/tags/rel_7/rtl/verilog/
23 Fifo corrected to be synthesizable. mohor 7835d 05h /can/tags/rel_7/rtl/verilog/
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7836d 09h /can/tags/rel_7/rtl/verilog/
21 Data is stored to fifo at the end of ack stage. mohor 7837d 01h /can/tags/rel_7/rtl/verilog/
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7837d 02h /can/tags/rel_7/rtl/verilog/

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