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[/] [can/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 60

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Rev	Log message	Author	Age	Path
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7781d 14h	/can/tags/rel_7/rtl/verilog/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7781d 15h	/can/tags/rel_7/rtl/verilog/
58	timescale.v is used for simulation only.	mohor	7782d 02h	/can/tags/rel_7/rtl/verilog/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7782d 02h	/can/tags/rel_7/rtl/verilog/
56	Doubled declarations removed.	mohor	7783d 01h	/can/tags/rel_7/rtl/verilog/
55	wire declaration added.	mohor	7783d 01h	/can/tags/rel_7/rtl/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7788d 03h	/can/tags/rel_7/rtl/verilog/
51	Xilinx RAM added.	mohor	7788d 04h	/can/tags/rel_7/rtl/verilog/
50	Top level signal names changed.	mohor	7788d 04h	/can/tags/rel_7/rtl/verilog/
48	Actel APA ram supported.	mohor	7791d 20h	/can/tags/rel_7/rtl/verilog/
47	Data is latched on read.	mohor	7791d 20h	/can/tags/rel_7/rtl/verilog/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7801d 18h	/can/tags/rel_7/rtl/verilog/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7801d 19h	/can/tags/rel_7/rtl/verilog/
41	Incomplete sensitivity list fixed.	mohor	7802d 04h	/can/tags/rel_7/rtl/verilog/
40	Typo fixed.	mohor	7802d 04h	/can/tags/rel_7/rtl/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7802d 04h	/can/tags/rel_7/rtl/verilog/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7803d 19h	/can/tags/rel_7/rtl/verilog/
35	Several registers added. Not finished, yet.	mohor	7806d 23h	/can/tags/rel_7/rtl/verilog/
33	abort_tx added.	mohor	7809d 04h	/can/tags/rel_7/rtl/verilog/
32	abort_tx added. Bit destuff fixed.	mohor	7809d 04h	/can/tags/rel_7/rtl/verilog/

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[/] [can/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 60

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