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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] - Rev 29

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Rev	Log message	Author	Age	Path
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7853d 07h	/can/tags/rel_9/bench/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7854d 00h	/can/tags/rel_9/bench/verilog/
26	Backup.	mohor	7858d 09h	/can/tags/rel_9/bench/verilog/
25	* empty log message *	mohor	7858d 11h	/can/tags/rel_9/bench/verilog/
24	backup.	mohor	7863d 01h	/can/tags/rel_9/bench/verilog/
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7877d 12h	/can/tags/rel_9/bench/verilog/
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7878d 05h	/can/tags/rel_9/bench/verilog/
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7878d 11h	/can/tags/rel_9/bench/verilog/
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7878d 13h	/can/tags/rel_9/bench/verilog/
17	Addresses corrected to decimal values (previously hex).	mohor	7879d 09h	/can/tags/rel_9/bench/verilog/
16	rx_fifo is now working.	mohor	7879d 14h	/can/tags/rel_9/bench/verilog/
15	Temporary version (backup).	mohor	7883d 08h	/can/tags/rel_9/bench/verilog/
14	rx fifo added. Not 100 % verified, yet.	mohor	7884d 04h	/can/tags/rel_9/bench/verilog/
13	Temporary files (backup).	mohor	7884d 11h	/can/tags/rel_9/bench/verilog/
11	Acceptance filter added.	mohor	7886d 00h	/can/tags/rel_9/bench/verilog/
10	Backup version.	mohor	7896d 22h	/can/tags/rel_9/bench/verilog/
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7898d 02h	/can/tags/rel_9/bench/verilog/
8	Testbench define file added. Clock divider register added.	mohor	7898d 10h	/can/tags/rel_9/bench/verilog/
7	Tripple sampling supported.	mohor	7899d 00h	/can/tags/rel_9/bench/verilog/
6	Commented lines removed.	mohor	7899d 02h	/can/tags/rel_9/bench/verilog/

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