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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] - Rev 61

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Rev	Log message	Author	Age	Path
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7794d 06h	/can/tags/rel_9/bench/verilog/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7794d 08h	/can/tags/rel_9/bench/verilog/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7794d 08h	/can/tags/rel_9/bench/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7800d 21h	/can/tags/rel_9/bench/verilog/
50	Top level signal names changed.	mohor	7800d 21h	/can/tags/rel_9/bench/verilog/
48	Actel APA ram supported.	mohor	7804d 13h	/can/tags/rel_9/bench/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7814d 22h	/can/tags/rel_9/bench/verilog/
38	Temporary backup version (still fully operable).	mohor	7816d 12h	/can/tags/rel_9/bench/verilog/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7816d 12h	/can/tags/rel_9/bench/verilog/
35	Several registers added. Not finished, yet.	mohor	7819d 16h	/can/tags/rel_9/bench/verilog/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7821d 22h	/can/tags/rel_9/bench/verilog/
31	Wishbone interface added.	mohor	7823d 11h	/can/tags/rel_9/bench/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7824d 18h	/can/tags/rel_9/bench/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7825d 10h	/can/tags/rel_9/bench/verilog/
26	Backup.	mohor	7829d 19h	/can/tags/rel_9/bench/verilog/
25	* empty log message *	mohor	7829d 22h	/can/tags/rel_9/bench/verilog/
24	backup.	mohor	7834d 11h	/can/tags/rel_9/bench/verilog/
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7848d 23h	/can/tags/rel_9/bench/verilog/
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7849d 15h	/can/tags/rel_9/bench/verilog/
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7849d 22h	/can/tags/rel_9/bench/verilog/

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] - Rev 61

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