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Rev Log message Author Age Path
161 New directory structure. root 5604d 14h /can/tags/rel_9/sim/rtl_sim/run/
98 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7686d 12h /can/tags/rel_9/sim/rtl_sim/run/
48 Actel APA ram supported. mohor 7804d 11h /can/tags/rel_9/sim/rtl_sim/run/
35 Several registers added. Not finished, yet. mohor 7819d 14h /can/tags/rel_9/sim/rtl_sim/run/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7824d 15h /can/tags/rel_9/sim/rtl_sim/run/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7825d 08h /can/tags/rel_9/sim/rtl_sim/run/
25 *** empty log message *** mohor 7829d 19h /can/tags/rel_9/sim/rtl_sim/run/
24 backup. mohor 7834d 09h /can/tags/rel_9/sim/rtl_sim/run/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7849d 21h /can/tags/rel_9/sim/rtl_sim/run/
16 rx_fifo is now working. mohor 7850d 22h /can/tags/rel_9/sim/rtl_sim/run/
14 rx fifo added. Not 100 % verified, yet. mohor 7855d 12h /can/tags/rel_9/sim/rtl_sim/run/
13 Temporary files (backup). mohor 7855d 19h /can/tags/rel_9/sim/rtl_sim/run/
11 Acceptance filter added. mohor 7857d 08h /can/tags/rel_9/sim/rtl_sim/run/
8 Testbench define file added. Clock divider register added. mohor 7869d 18h /can/tags/rel_9/sim/rtl_sim/run/
5 Synchronization working. mohor 7870d 20h /can/tags/rel_9/sim/rtl_sim/run/
2 Initial mohor 7875d 17h /can/tags/rel_9/sim/rtl_sim/run/

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