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[/] [can/] [trunk/] [bench/] - Rev 127

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Rev Log message Author Age Path
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7652d 22h /can/trunk/bench/
119 Artisan RAMs added. mohor 7694d 08h /can/trunk/bench/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7758d 03h /can/trunk/bench/
68 CAN inturrupt is active low. mohor 7841d 07h /can/trunk/bench/
63 ALE changes on negedge of clk. mohor 7852d 23h /can/trunk/bench/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7855d 13h /can/trunk/bench/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7855d 14h /can/trunk/bench/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7855d 14h /can/trunk/bench/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7862d 03h /can/trunk/bench/
50 Top level signal names changed. mohor 7862d 04h /can/trunk/bench/
48 Actel APA ram supported. mohor 7865d 20h /can/trunk/bench/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7876d 04h /can/trunk/bench/
38 Temporary backup version (still fully operable). mohor 7877d 18h /can/trunk/bench/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7877d 18h /can/trunk/bench/
35 Several registers added. Not finished, yet. mohor 7880d 22h /can/trunk/bench/
34 Errors monitoring improved. arbitration_lost improved. mohor 7883d 04h /can/trunk/bench/
31 Wishbone interface added. mohor 7884d 18h /can/trunk/bench/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7886d 00h /can/trunk/bench/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7886d 16h /can/trunk/bench/
26 Backup. mohor 7891d 01h /can/trunk/bench/

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