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[/] [can/] [trunk/] [bench/] [verilog/] - Rev 163

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Rev Log message Author Age Path
161 New directory structure. root 5718d 01h /can/trunk/bench/verilog/
160 New tests for testing the bus-off. igorm 6767d 07h /can/trunk/bench/verilog/
158 Fixing overrun problems. igorm 7055d 10h /can/trunk/bench/verilog/
140 I forgot to thange one signal name. igorm 7535d 03h /can/trunk/bench/verilog/
139 Signal bus_off_on added. igorm 7535d 03h /can/trunk/bench/verilog/
130 mbist signals updated according to newest convention markom 7688d 14h /can/trunk/bench/verilog/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7704d 23h /can/trunk/bench/verilog/
119 Artisan RAMs added. mohor 7746d 10h /can/trunk/bench/verilog/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7810d 05h /can/trunk/bench/verilog/
68 CAN inturrupt is active low. mohor 7893d 09h /can/trunk/bench/verilog/
63 ALE changes on negedge of clk. mohor 7905d 01h /can/trunk/bench/verilog/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7907d 14h /can/trunk/bench/verilog/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7907d 16h /can/trunk/bench/verilog/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7907d 16h /can/trunk/bench/verilog/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7914d 05h /can/trunk/bench/verilog/
50 Top level signal names changed. mohor 7914d 05h /can/trunk/bench/verilog/
48 Actel APA ram supported. mohor 7917d 21h /can/trunk/bench/verilog/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7928d 06h /can/trunk/bench/verilog/
38 Temporary backup version (still fully operable). mohor 7929d 20h /can/trunk/bench/verilog/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7929d 20h /can/trunk/bench/verilog/

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