OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [bench/] [verilog/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7855d 10h /can/trunk/bench/verilog/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7861d 23h /can/trunk/bench/verilog/
50 Top level signal names changed. mohor 7861d 23h /can/trunk/bench/verilog/
48 Actel APA ram supported. mohor 7865d 16h /can/trunk/bench/verilog/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7876d 00h /can/trunk/bench/verilog/
38 Temporary backup version (still fully operable). mohor 7877d 14h /can/trunk/bench/verilog/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7877d 14h /can/trunk/bench/verilog/
35 Several registers added. Not finished, yet. mohor 7880d 18h /can/trunk/bench/verilog/
34 Errors monitoring improved. arbitration_lost improved. mohor 7883d 00h /can/trunk/bench/verilog/
31 Wishbone interface added. mohor 7884d 14h /can/trunk/bench/verilog/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 7885d 20h /can/trunk/bench/verilog/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.
mohor 7886d 12h /can/trunk/bench/verilog/
26 Backup. mohor 7890d 21h /can/trunk/bench/verilog/
25 *** empty log message *** mohor 7891d 00h /can/trunk/bench/verilog/
24 backup. mohor 7895d 13h /can/trunk/bench/verilog/
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).
mohor 7910d 01h /can/trunk/bench/verilog/
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7910d 17h /can/trunk/bench/verilog/
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7911d 00h /can/trunk/bench/verilog/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7911d 01h /can/trunk/bench/verilog/
17 Addresses corrected to decimal values (previously hex). mohor 7911d 21h /can/trunk/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.