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[/] [can/] [trunk/] [bench/] [verilog/] - Rev 60

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Rev	Log message	Author	Age	Path
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7798d 05h	/can/trunk/bench/verilog/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7798d 05h	/can/trunk/bench/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 18h	/can/trunk/bench/verilog/
50	Top level signal names changed.	mohor	7804d 18h	/can/trunk/bench/verilog/
48	Actel APA ram supported.	mohor	7808d 10h	/can/trunk/bench/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7818d 19h	/can/trunk/bench/verilog/
38	Temporary backup version (still fully operable).	mohor	7820d 09h	/can/trunk/bench/verilog/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7820d 09h	/can/trunk/bench/verilog/
35	Several registers added. Not finished, yet.	mohor	7823d 13h	/can/trunk/bench/verilog/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7825d 19h	/can/trunk/bench/verilog/
31	Wishbone interface added.	mohor	7827d 08h	/can/trunk/bench/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7828d 15h	/can/trunk/bench/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7829d 07h	/can/trunk/bench/verilog/
26	Backup.	mohor	7833d 16h	/can/trunk/bench/verilog/
25	* empty log message *	mohor	7833d 19h	/can/trunk/bench/verilog/
24	backup.	mohor	7838d 08h	/can/trunk/bench/verilog/
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7852d 20h	/can/trunk/bench/verilog/
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7853d 12h	/can/trunk/bench/verilog/
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7853d 19h	/can/trunk/bench/verilog/
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7853d 20h	/can/trunk/bench/verilog/

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[/] [can/] [trunk/] [bench/] [verilog/] - Rev 60

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