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[/] [can/] [trunk/] [rtl/] - Rev 59

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Rev Log message Author Age Path
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7795d 03h /can/trunk/rtl/
58 timescale.v is used for simulation only. mohor 7795d 15h /can/trunk/rtl/
57 Mux used for clkout to avoid "gated clocks warning". mohor 7795d 15h /can/trunk/rtl/
56 Doubled declarations removed. mohor 7796d 14h /can/trunk/rtl/
55 wire declaration added. mohor 7796d 14h /can/trunk/rtl/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7801d 16h /can/trunk/rtl/
51 Xilinx RAM added. mohor 7801d 16h /can/trunk/rtl/
50 Top level signal names changed. mohor 7801d 16h /can/trunk/rtl/
48 Actel APA ram supported. mohor 7805d 08h /can/trunk/rtl/
47 Data is latched on read. mohor 7805d 08h /can/trunk/rtl/
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7815d 07h /can/trunk/rtl/
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7815d 08h /can/trunk/rtl/
41 Incomplete sensitivity list fixed. mohor 7815d 16h /can/trunk/rtl/
40 Typo fixed. mohor 7815d 16h /can/trunk/rtl/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7815d 16h /can/trunk/rtl/
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7817d 07h /can/trunk/rtl/
35 Several registers added. Not finished, yet. mohor 7820d 11h /can/trunk/rtl/
33 abort_tx added. mohor 7822d 17h /can/trunk/rtl/
32 abort_tx added. Bit destuff fixed. mohor 7822d 17h /can/trunk/rtl/
31 Wishbone interface added. mohor 7824d 06h /can/trunk/rtl/

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