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[/] [can/] [trunk/] [rtl/] [verilog/] - Rev 137

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Rev Log message Author Age Path
137 Header changed. mohor 7418d 22h /can/trunk/rtl/verilog/
136 Error counters changed. mohor 7418d 22h /can/trunk/rtl/verilog/
135 Header changed. mohor 7418d 22h /can/trunk/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7526d 19h /can/trunk/rtl/verilog/
130 mbist signals updated according to newest convention markom 7533d 06h /can/trunk/rtl/verilog/
129 Error counters changed. mohor 7549d 15h /can/trunk/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7550d 11h /can/trunk/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7554d 17h /can/trunk/rtl/verilog/
124 ALTERA_RAM supported. mohor 7575d 00h /can/trunk/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7582d 05h /can/trunk/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7591d 02h /can/trunk/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7591d 02h /can/trunk/rtl/verilog/
115 Artisan ram instances added. simons 7596d 20h /can/trunk/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7623d 21h /can/trunk/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7625d 21h /can/trunk/rtl/verilog/
110 Fixed according to the linter. mohor 7625d 21h /can/trunk/rtl/verilog/
109 Fixed according to the linter. mohor 7625d 22h /can/trunk/rtl/verilog/
108 Fixed according to the linter. mohor 7625d 23h /can/trunk/rtl/verilog/
107 Fixed according to the linter. mohor 7625d 23h /can/trunk/rtl/verilog/
106 Unused signal removed. mohor 7631d 21h /can/trunk/rtl/verilog/

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