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[/] [can/] [trunk/] [rtl/] [verilog/] - Rev 145

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Rev Log message Author Age Path
145 Arbitration bug fixed. igorm 7164d 21h /can/trunk/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7311d 13h /can/trunk/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7330d 12h /can/trunk/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7424d 13h /can/trunk/rtl/verilog/
137 Header changed. mohor 7424d 14h /can/trunk/rtl/verilog/
136 Error counters changed. mohor 7424d 14h /can/trunk/rtl/verilog/
135 Header changed. mohor 7424d 14h /can/trunk/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7532d 11h /can/trunk/rtl/verilog/
130 mbist signals updated according to newest convention markom 7538d 22h /can/trunk/rtl/verilog/
129 Error counters changed. mohor 7555d 07h /can/trunk/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7556d 03h /can/trunk/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7560d 09h /can/trunk/rtl/verilog/
124 ALTERA_RAM supported. mohor 7580d 15h /can/trunk/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7587d 21h /can/trunk/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7596d 18h /can/trunk/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7596d 18h /can/trunk/rtl/verilog/
115 Artisan ram instances added. simons 7602d 12h /can/trunk/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7629d 13h /can/trunk/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7631d 13h /can/trunk/rtl/verilog/
110 Fixed according to the linter. mohor 7631d 13h /can/trunk/rtl/verilog/

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