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[/] [can/] [trunk/] [rtl/] [verilog/] - Rev 149

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Rev Log message Author Age Path
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7165d 07h /can/trunk/rtl/verilog/
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7167d 14h /can/trunk/rtl/verilog/
145 Arbitration bug fixed. igorm 7167d 19h /can/trunk/rtl/verilog/
143 Bit acceptance_filter_mode was inverted. igorm 7314d 11h /can/trunk/rtl/verilog/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7333d 10h /can/trunk/rtl/verilog/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7427d 11h /can/trunk/rtl/verilog/
137 Header changed. mohor 7427d 12h /can/trunk/rtl/verilog/
136 Error counters changed. mohor 7427d 12h /can/trunk/rtl/verilog/
135 Header changed. mohor 7427d 12h /can/trunk/rtl/verilog/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7535d 09h /can/trunk/rtl/verilog/
130 mbist signals updated according to newest convention markom 7541d 20h /can/trunk/rtl/verilog/
129 Error counters changed. mohor 7558d 05h /can/trunk/rtl/verilog/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7559d 01h /can/trunk/rtl/verilog/
125 Synchronization changed, error counters fixed. mohor 7563d 07h /can/trunk/rtl/verilog/
124 ALTERA_RAM supported. mohor 7583d 13h /can/trunk/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7590d 19h /can/trunk/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7599d 16h /can/trunk/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7599d 16h /can/trunk/rtl/verilog/
115 Artisan ram instances added. simons 7605d 10h /can/trunk/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7632d 11h /can/trunk/rtl/verilog/

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