OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [sim/] [rtl_sim/] [run/] - Rev 163

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 New directory structure. root 5602d 17h /can/trunk/sim/rtl_sim/run/
159 *** empty log message *** igorm 6940d 00h /can/trunk/sim/rtl_sim/run/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7364d 21h /can/trunk/sim/rtl_sim/run/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7589d 16h /can/trunk/sim/rtl_sim/run/
119 Artisan RAMs added. mohor 7631d 02h /can/trunk/sim/rtl_sim/run/
48 Actel APA ram supported. mohor 7802d 14h /can/trunk/sim/rtl_sim/run/
35 Several registers added. Not finished, yet. mohor 7817d 16h /can/trunk/sim/rtl_sim/run/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7822d 18h /can/trunk/sim/rtl_sim/run/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7823d 10h /can/trunk/sim/rtl_sim/run/
25 *** empty log message *** mohor 7827d 22h /can/trunk/sim/rtl_sim/run/
24 backup. mohor 7832d 11h /can/trunk/sim/rtl_sim/run/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7847d 23h /can/trunk/sim/rtl_sim/run/
16 rx_fifo is now working. mohor 7849d 00h /can/trunk/sim/rtl_sim/run/
14 rx fifo added. Not 100 % verified, yet. mohor 7853d 15h /can/trunk/sim/rtl_sim/run/
13 Temporary files (backup). mohor 7853d 22h /can/trunk/sim/rtl_sim/run/
11 Acceptance filter added. mohor 7855d 10h /can/trunk/sim/rtl_sim/run/
8 Testbench define file added. Clock divider register added. mohor 7867d 20h /can/trunk/sim/rtl_sim/run/
5 Synchronization working. mohor 7868d 22h /can/trunk/sim/rtl_sim/run/
2 Initial mohor 7873d 20h /can/trunk/sim/rtl_sim/run/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.