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[/] [common/] [tags/] [rel_12/] [generic_memories/] - Rev 47

Rev	Log message	Author	Age	Path
47		linus	5555d 08h	/common/tags/rel_12/generic_memories/
42	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7939d 10h	/common/tags/rel_12/generic_memories/
41	Changed synthesizeable FPGA memory implementation. Fixed some issues with Xilinx BlockRAM	rherveille	7939d 10h	/common/tags/rel_12/generic_memories/
38	Undeleted	mohor	8006d 03h	/common/tags/rel_12/generic_memories/
36	minor changes: unified with all common rams	samg	8262d 18h	/common/tags/rel_12/generic_memories/
35	corrected output: output not valid if ce low	samg	8262d 23h	/common/tags/rel_12/generic_memories/
34	added valid checks to behvioral model	samg	8262d 23h	/common/tags/rel_12/generic_memories/
33	added checks and task in behavioral section	samg	8264d 00h	/common/tags/rel_12/generic_memories/
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8318d 08h	/common/tags/rel_12/generic_memories/