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[/] [common/] [tags/] [rel_19/] [generic_memories/] [rtl/] [verilog/] - Rev 47

Rev	Log message	Author	Age	Path
47		linus	5573d 02h	/common/tags/rel_19/generic_memories/rtl/verilog/
43	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7957d 04h	/common/tags/rel_19/generic_memories/rtl/verilog/
41	Changed synthesizeable FPGA memory implementation. Fixed some issues with Xilinx BlockRAM	rherveille	7957d 04h	/common/tags/rel_19/generic_memories/rtl/verilog/
38	Undeleted	mohor	8023d 21h	/common/tags/rel_19/generic_memories/rtl/verilog/
36	minor changes: unified with all common rams	samg	8280d 12h	/common/tags/rel_19/generic_memories/rtl/verilog/
35	corrected output: output not valid if ce low	samg	8280d 17h	/common/tags/rel_19/generic_memories/rtl/verilog/
34	added valid checks to behvioral model	samg	8280d 17h	/common/tags/rel_19/generic_memories/rtl/verilog/
33	added checks and task in behavioral section	samg	8281d 18h	/common/tags/rel_19/generic_memories/rtl/verilog/
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8336d 02h	/common/tags/rel_19/generic_memories/rtl/verilog/