URL https://opencores.org/ocsvn/common/common/trunk

Subversion Repositories common

[/] [common/] [trunk/] - Rev 32

Rev	Log message	Author	Age	Path
32	no message	bbeaver	8271d 15h	/common/trunk/
31	no message	bbeaver	8275d 15h	/common/trunk/
30	no message	bbeaver	8276d 14h	/common/trunk/
29	got timing checks mostly correct No functional stuff yet	bbeaver	8276d 15h	/common/trunk/
28	no message	bbeaver	8277d 15h	/common/trunk/
27	no message	bbeaver	8278d 15h	/common/trunk/
26	no message	bbeaver	8279d 14h	/common/trunk/
25	no message	bbeaver	8280d 15h	/common/trunk/
24	no message	bbeaver	8282d 17h	/common/trunk/
23	no message	bbeaver	8283d 16h	/common/trunk/
22	no message	bbeaver	8283d 19h	/common/trunk/
21	Added bookmarks.	lampret	8284d 09h	/common/trunk/
20	Some minor fixes. Document is now official version.	lampret	8284d 09h	/common/trunk/
19	no message	bbeaver	8285d 17h	/common/trunk/
18	no message	bbeaver	8286d 15h	/common/trunk/
17	Fixed link to specification_template.dot	lampret	8286d 23h	/common/trunk/
16	Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word.	lampret	8287d 00h	/common/trunk/
15	no message	bbeaver	8306d 21h	/common/trunk/
14	adding beginning LPM files	bbeaver	8318d 17h	/common/trunk/
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8324d 17h	/common/trunk/