OpenCores
URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] - Rev 26

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 v1.4 PRODUCTION fpga_is_funny 2252d 21h /cpu6502_true_cycle/trunk/
25 fpga_is_funny 2254d 07h /cpu6502_true_cycle/trunk/
24 Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
simulation with RTI and in a real environment by customer.
Removed directory ./verilog_TRIAL from source.		 fpga_is_funny 5358d 20h /cpu6502_true_cycle/trunk/
22 fpga_is_funny 5358d 21h /cpu6502_true_cycle/trunk/
18 New directory structure. root 5729d 22h /cpu6502_true_cycle/trunk/
17 CORRECTED "RTI" (wrong: use of stack pointer)
RENAME all states of "FSM Execution Unit" for better reading
(90%) Finish working for Specification of cpu6502_tc		 fpga_is_funny 5742d 00h /trunk/
16 CORRECTED "RTI" (wrong: use of stack pointer)
RENAME all states of "FSM Execution Unit" for better reading
(90%) Finish working for Specification of cpu6502_tc		 fpga_is_funny 5742d 00h /trunk/
15 CORRECTED "RTI" (wrong: use of stack pointer)
RENAME all states of "FSM Execution Unit" for better reading
(90%) Finish working for Specification of cpu6502_tc		 fpga_is_funny 5742d 00h /trunk/
14 More optimizations...
- Second Phaze of removing unused nets & registers
- Added Verilog source on demand by some customers (for trial use)		 fpga_is_funny 5788d 21h /trunk/
13 DELETED directory cpu6502_true_cycle/doc/HTML - use the HTML.RAR file instead fpga_is_funny 5793d 18h /trunk/
12 no message fpga_is_funny 5793d 18h /trunk/
11 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads
from $02FF and $0200, instead of $02FF and $0300)		 fpga_is_funny 5793d 20h /trunk/
9 This commit was generated by cvs2svn to compensate for changes in r8, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5793d 20h /trunk/
7 This commit was generated by cvs2svn to compensate for changes in r6, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5793d 21h /trunk/
5 Bugfixes for all relationchips with interrupts BRK, IRQ and NMI.
The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down.
The "B" status flag was never set within BRK.
The relationchip between addresses and data while writing onto the stack was badly misalligned.		 fpga_is_funny 6056d 00h /trunk/
4 Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release) fpga_is_funny 6064d 21h /trunk/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 6064d 22h /trunk/
1 Standard project directories initialized by cvs2svn. 6064d 22h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.